The L0 bootloader scripts for the 2700HGV and the 2701HGV-C have been extracted from the boot ROMs.
The bootscript contents have been cross-referenced against the documentation for two other CPUs with TM3260 cores. Those CPUs are the PNX15xx  and the PNX8526 .
From that analysis, the bootscripts for the 2Wire 2700HGV and the 2701HGV-C, both Ares boards, are understood to some degree.
A tentative memory map for the 2Wire Ares CPU is suggested below..
Since the memory map is based only on the bootscript contents and on the similarities of the Ares to the PNX15xx and the PNX85xx, and specifically the MMIO registers used to define apertures, nothing is known for sure.
So this is very much a work in progress and may be revised as more is understood of the architecture.
In particular, a number of important things are still not clear:
Another bus architecture can be identified from the MMIO register access in the 2Wire Ares bootscripts. The bus is believed to be a Peripheral Interface (PI) bus.
From analyzing the bootscripts, the bus appears to have a (DMA) aperture which maps to the whole DRAM aperture (address space 0×4000 0000 to 0×4400 0000).
The purpose of this bus is not known, nor have the peripherals been identified which utilize it. However, the peripherals could be the xDSL Analog Front End, and/or the 802.11 chipset. The datasheets for these devices and their pinouts on the 2Wire boards would be insightful.
The bootscripts can tell us other things: We now know the PCI bus settings for the boards, and we can determine the m, n and p values for configuring the PLL settings.
The bootscripts indicate that the DRAM cacheable limit is at the top of the DRAM aperture. In other words, all 64MB of the DRAM is cacheable.
The Ares’ bootscripts also indicate the presence of an MMI Arbitration module. This arbitrates peripheral access to the main memory bus. The Ares’ module looks similar in function to the arbitration module in the PNX8526.